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6
M-986-2A1
Rev. 3
Serial Port Timing
Parameter
Min
Nom
Max
Unit
t
d (CH-FR)
Internal framing delay from SCLK rising edge
-
70
ns
t
d (DX1-CL)
DX bit 1 valid before SCLK falling edge
20
-
ns
t
d (DX2-CL)
DX bit 2 valid before SCLK falling edge
20
-
ns
t
h (DX)
DX hold time after SCLK falling edge
244
-
ns
t
su (DR)
DR setup time before SCLK falling edge
20
-
ns
t
h (DR)
DR hold time after SCLK falling edge
20
-
ns
t
c (SCLK)
Serial port clock cycle time
399
488.28
4770
ns
t
f (SCLK)
Serial port clock fall time
-
30
ns
t
r (SCLK)
Serial port clock rise time
-
30
ns
t
w (SCLKL)
Serial port clock low-pulse duration*
220
244.14
2500
ns
t
w (SCLKH)
Serial port clock high-pulse duration*
220
244.14
2500
ns
t
su (FS)
FSX/FSR setup time before SCLK falling edge
100
-
ns
* The duty cycle of the serial port clock must be within 45% to 55%.
External Frequency Specifications
Parameter
Min
Nom
Max
Unit
t
C(MC)
Master clock cycle time
48.818
48.828
48.838
ns
t
r(MC)
Rise time master clock input
-
5
10
ns
t
f(MC)
Pulse duration master clock
20
-
ns
Recommended Operating Conditions
Parameter
Min
Nom
Max
Unit
V
CC
Supply voltage
4.75
5
5.25
V
SS
Supply voltage
-
0
-
V
IH
High-level input voltage
All inputs except CLKIN
2
-
V
CLKIN
3
-
V
MC/PM
2.2
-
V
IL
Low-level input voltage
All inputs except MC/MP
-
0.8
V
MC/MP
-
0.6
V
I
OH
High-level output current (all outputs)
-
-300
A
I
OL
Low-level output current (all outputs)
-
2
mA
T
A
Operating free-air temperature
0
-
70
C
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